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Technical talk on Enhancing FPGA based machine learning overcoming challenging for optional performance
Overview
IEEE Student Branch BITM conducted a technical talk on “Enhancing FPGA based machine learning: overcoming challenging for optional performance” by, Dr. Luca Di Nunzio, university of Rome Tor Vergata, Rome Italy and Dr. Parameshachari briefed the students about IEEE, in the presence of Dr. Yadavalli Basavaraj (principal, BITM), Dr. Yashwanth Bhupal (Director, BITM), Dr. Y J Prithviraj Bhupal (Deputy Director), Dr. V C Patil (Dean(R&D)) Dr. K M Sadyojatha (HOD, ECE, BTIM) and Dr. Abdul Lateef Haroon P.S (IEEE SB Counsellor, BITM).
Dr. Luca Di Nunzio, gave the insights about the FPGA technology that is very enhancing which is based on the machine learning, and also gave an information for overcoming the challenges that are required for optional performance. Along with this Dr. Parameshachari, prof, dept. of ECE, Nitte Meenakshi institute of technology, Bengaluru. Empowered the students by briefing about the benefits IEEE holds.
Objectives
The IEEE Student Branch BITM organized a technical talk on “Enhancing FPGA-Based Machine Learning: Overcoming Challenges for Optimal Performance” by Dr. Luca Di Nunzio from the University of Rome Tor Vergata. The session, attended by esteemed dignitaries, also featured a briefing on IEEE's benefits by Dr. Parameshachari.
